The present disclosures relate generally to semiconductor devices, and more particularly, to a transistor structure and method of making a transistor structure with stress modification and capacitive reduction features in a width direction.
A narrow width PFET drive current enhancement on the order of approximately 15 to 40 percent (15–40%) has been observed with narrow width PFET devices on a <100> orientation SOI substrate. Such an enhancement is believed related to a stress induced mobility enhancement. However, there exist one or more limiting factors that prevent taking advantage of this drive current improvement. First, in a typical high performance product in 0.13 micron technology, a significant amount of PFET transistors are designed at a relatively wide width, for example, having a peak PFET width distribution around 3.3 μm. As a result, such wide width PFET devices are unable to benefit from the narrow width PFET enhancement. Secondly, to enable a circuit to function, an NFET to PFET drive current ratio should be maintained within a certain range, i.e., typically around 2. Too strong of a PFET drive current may not be a good thing for the circuit, since the strong PFET drive current has the potential to cause circuit failure.
Accordingly, it would be desirable to provide an improved transistor structure and method of making the same for overcoming the problems in the art.